The sampling cycle is different from the conversion cycle when it comes to the associated system priority, the respective mode, and the cycle time. The traced data of the conversion cycle are processed in a lower-value sampling cycle as a function of the channel configuration.
Channel data are processed in the following order:
oLow pass filter (opt.)
oScaling (kx + d), limit values
oError statistics counter (opt.)
oMinimum/maximum analysis (opt.)
oHysteresis comparator
Channel error information and the results of the hysteresis comparator are summed up in a register. Using the result of the comparison, two independent events are to be triggered: Trace Trigger and Trace Sample. If the sampling cycle is triggered by the conversion cycle before the data processing (as well as the processing of the converter events) of the previous cycle has been completed, a sampling cycle time violation is detected (conversion cycle catches up with the sampling cycle).Using this register, the sampling cycle can be improved (resolution capacity = 1 μs).
Depending on the system configuration, fast sampling cycles may lead to a sampling cycle time violation. The shortest possible cycle time is 50 μs.
