The system distinguishes conversion cycle and sampling cycle.
The AD converter hardware is queried during the conversion cycle. The cycle is derived from a pulse-width modulated signal. This pulse-width modulated signal is connected with the start signal of the AD converter (sample and hold). The basic data of the AD converter are stored alternatingly in the sampling memory area. If the tracing is completed, the sampling cycle is triggered (sampling cycle follows on the conversion cycle). To ensure that the AD conversion is executed without any delay in time, a high system priority is required for the conversion cycle. In the synchronized mode, the conversion cycle (PWM generator) is adapted.
The conversion cycle time is derived from the sampling cycle time settings. As a function of the alternating conversion mode, the system calculates the conversion cycle (pulse width modulation period).
Alternate gain: conversion cycle time = sampling cycle time / 2
