The counter status of the rising edges is recorded with a defined offset (max. 60 μsec) in relation to the network SyncIn and transmitted in the same cycle.
For cycle times of < 150 μsec, sampling is executed in the half-cycle.The event counter is generated via SW in Timerinterrupt with a sample rate of 100 μsec without filter or 200 μsec with filter by counting the rising edges.
From this, a maximum theoretical counter frequency of 2500 kHz or 1250 kHz results at a minimum of four samplings.
Due to jitters resulting from the communication, these values have to be reduced by the factor 2 (that is, approx. 1 kHz or 500 Hz).
The time between the rising and falling edges of the gate input is recorded with an internal frequency of 48 MHz.
The result is checked for overflow (FFFF hex) and corrected in accordance with the defined prescalers.
The recovery time between the measurements has to be > 100 μsec.
The measured result is transferred to the SyncIn buffer during the falling edge.
|
Bit |
Description |
|---|---|
|
0–3 |
0000 = Event counter by using HW counter (only in the case of event counter-measurement) 0001 = Event counter by using SW after the input filter (only in the case of event counter-measurement) Scaler for gating time measurement: 0000 = Measurement base 48 MHz 0001 = Measurement base 3 MHz 0010 = Measurement base 187.5 kHz 0011 = Measurement base 24 MHz 0100 = Measurement base 12 MHz 0101 = Measurement base 6 MHz 0110 = Measurement base 1.5 MHz 0111 = Measurement base 750 kHz 1000 = Measurement base 375 kHz |
|
4 |
0 |
|
5 |
0 = No effect on counter 1 = Delete counter |
|
6–7 |
00 = Event counter-measurement 01 = Gating time measurement |
