Digital mixed module 24 Vdc pre-configured with:
oFour oversampled inputs
oFour time-stamped outputs
Parameterizing the Device Object Corresponding to the Module
Step |
Action |
---|---|
1 |
Add module in the Devices tree under a Sercos III bus interface (TM5NS31). |
2 |
Double-click on the module in the Devices tree. Result: The device editor is opened and the index cards Sercos III Module I/O Mapping, User Parameter, and Information are displayed. |
Index Card Sercos III Module I/O Mapping
The input and output channels of the module are mapped to project variables that are used by the application.
I/O mapping channel |
Meaning |
Data type |
---|---|---|
ErrorQuit ErrorQuit_2 |
Acknowledgement of the detected active errors (QuitOutputControlError, QuitOutputCopyError) Refer to Controlling the Oversampled Outputs. |
BYTE |
OversampleControl |
Control of the oversample functionality (OversampleEnable, OversampleControlCopyActive) Refer to Controlling the Oversampled Outputs. |
BYTE |
EdgeGen01Enable...EdgeGen04Enable |
Set to 1 to enable the time-stamped output unit. Set to 0 to disable the time-stamped output unit. |
BYTE |
EdgeGen01Sequence...EdgeGen04Sequence |
If new time-stamped data is to be applied to the module, the sequence number must be increased. For each pulse data transmitted to the time-stamped unit, this sequence must be increased by 1. |
BYTE |
EdgeGen01Timestamp...EdgeGen04Timestamp |
The absolute time-stamp when the rising edge is generated. The time-stamp can be calculated with the SystemInterface function FC_GetRelativeTM5Nettime16Bit (). |
WORD |
EdgeGen01Offset2...EdgeGen04Offset2 |
Offset in μs when the falling edge is generated. The module generates the rising edge at the absolute time EdgeGen0xTimestamp + EdgeGen0xOffset2. |
WORD |
ModuleOK |
Value for OK = 245 Bit 0: DcOk, Power supply in the valid range: 0 = Invalid, 1 = Valid Bit 1: Reserved Bit 2: NetworkOK, TM5 bus: 0 = Not OK, 1 = OK Bit 3: I/O Data valid, I/O Data: 0 = Valid, 1 = Invalid Bit 4 - 7: Reserved |
BYTE |
ErrorState |
State of the detected active errors Refer to Controlling the Oversampled Outputs. Bit 1 - 4: Reserved Bit 5: OutputControlError, 0 = No error detected, 1 = Error detected Bit 6: OutputCopyError, 0 = No error detected, 1 = Error detected Bit 7 - 8: Reserved |
BYTE |
ErrorState_2 |
State of the detected active errors Bit1: EdgeGen01Error, 0 = No error detected, 1 = Error detected Bit2: EdgeGen01Warning, 0 = No warning detected, 1 = Warning detected Bit3: EdgeGen02Error, 0 = No error detected, 1 = Error detected Bit4: EdgeGen02Warning, 0 = No warning detected, 1 = Warning detected Bit5: EdgeGen03Error, 0 = No error detected, 1 = Error detected Bit6: EdgeGen03Warning, 0 = No warning detected, 1 = Warning detected Bit7: EdgeGen04Error, 0 = No error detected, 1 = Error detected Bit8: EdgeGen04Warning, 0 = No warning detected, 1 = Warning detected |
BYTE |
DigitalInput01-08 |
Values of the input channels 01 to 08 |
BYTE |
OversampleInputCycle |
Oversampling input buffer address of the I/O module Refer to Controlling the Oversampled Outputs. |
BYTE |
OversampleInput01Sample1_8...OversampleInput04Sample1_8 |
8 bits oversampling input data for channel 01, which is written to the oversampling output buffer. |
BYTE |
EdgeGen01EnableReadback...EdgeGen04EnableReadback |
Reads back the value of EdgeGen0xEnable in the time-stamped unit in the module. |
BYTE |
EdgeGen01SequenceReadback...EdgeGen04SequenceReadback |
Reads back the value of EdgeGen0xSequence in the timestamped unit in the module. This readback value shows the EdgeGen0xSequence if the timestamped unit accepted the given pulse (EdgeGen0xTimestamp + EdgeGen0xOffset2). If the EdgeGenUnit0xTimestampFifoLim is exceeded, the EdgeGen0xSequenceReadback shows the last EdgeGen0xSequence that was accepted. |
BYTE |
The change over between numeric and symbolic values takes place via the check box Symbolic values.
Name |
Meaning |
Default value |
Data type |
---|---|---|---|
Cycle time (200...2000 [μs/8]) |
TM5SDM8DTS cycle time Refer to Configuration of Timing Parameters. |
1000 |
BitArea |
Cycle prescaler (2...128) |
Value to prescale the system time Refer to Configuration of Timing Parameters. |
2 |
BitArea |
Oversample cycle |
System timer (2) or prescaled system timer (3) Refer to Configuration of Timing Parameters. |
2 (system timer) |
BYTE |
Edge generation cycle |
Defines how often the time-stamped output unit can generate pulse configurations. In one Edge generation cycle, only one pulse configuration (consisting of one rising edge and one falling edge) can be generated. |
2 (system timer) |
BYTE |