You can configure the priority of each task between 0 and 31 (0 is the highest priority, 31 is the lowest). Each task must have a unique priority. Assigning the same priority to more than one task leads to a build error.
oPriority 0 to 24: Controller tasks. Assign these priorities to tasks with a high availability requirement.
oPriority 25 to 31: Background tasks. Assign these priorities to tasks with a low availability requirement.
Task Priorities of Embedded I/Os
When a task cycle starts, it can interrupt any task with lower priority (task preemption). The interrupted task resumes when the higher priority task cycle is finished.
NOTE: If the same input is used in different tasks the input image may change during the task cycle of the lower priority task.
To improve the likelihood of proper output behavior during multitasking, a build error message is displayed if outputs in the same byte are used in different tasks.
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UNINTENDED EQUIPMENT OPERATION |
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Map your inputs so that tasks do not alter the input images in an unexpected manner. |
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Failure to follow these instructions can result in death, serious injury, or equipment damage. |
Task Priorities of TM2/TM3 Modules and CANopen I/Os
You can select the task that drives TM3 and CANopen physical exchanges. In the PLC settings, select Bus cycle task to define the task for the exchange. By default, the task is set to MAST. This definition at the controller level can be overridden by the I/O bus configuration. During the read and write phases, all physical I/Os are refreshed at the same time. TM3/TM2 and CANopen data is copied into a virtual I/O image during a physical exchanges phase, as shown in this figure:
Inputs are read from the I/O image table at the beginning of the task cycle. Outputs are written to the I/O image table at the end of the task.
NOTE: Event tasks cannot drive the TM3/TM2 bus cycle.
