This register is used by the module to indicate sending and receiving readiness, data received, and to send frame data to the superordinate system.
Bit |
Description |
---|---|
0...2 |
0...7 = Consecutive receiver sequence number |
3 |
0 = Receiver connection establishment requested by module 1 = Receiver data exchange is enabled |
4...6 |
0...7 = Transmitter sequence number acknowledgment |
7 |
0 = Transmitter connection establishment requested by module 1 = Transmitter data exchange is enabled |
Consecutive Receiver Sequence Number
If data from the module are available, they are created in the Input MTU block and the sequence number sent to the superordinate system incremented. By default (see also Block Forward), a new sequence number with new data from the module is only put into the Input MTU block once the current sequence number has been acknowledged by the OutputSequence. This is done to signal to the module that the Input MTU block has been read and can now be overwritten. This counter is also incremented to detect status changes in connection establishment or termination.
Receiver Connection Establishment / Data Exchange
With this status bit, the module signals whether the interface is ready to receive and is synchronized with the superordinate system. The interface is ready to receive only after synchronization (see also Synchronization of the Sending and Receiving Readiness).
This status bit should be regularly monitored, as if transfer problems occur or noncompliance with the sequence acknowledgment is detected, the module itself can disconnect the connection. If so, synchronization must be repeated.
Transmitter Sequence Number Acknowledgment
Indicates which sequence is to be sent from the OutputSequence the module received. The module thereby indicates that the data have been read from the Output MTU block and copied to the buffer. The Output MTU can therefore be overwritten with new transmission data.
Transmit Connection Establishment / Data Exchange
This bit is the status feedback from the module that the sending direction is active and synchronized (see also Synchronization of the Sending and Receiving Readiness). Therefore, data destined for the interface can now be sent.