Oversampled Outputs

Contents of This Topic

This topic contains the following information:

oGeneral information on oversampled outputs

oInitializing the handling of the oversampled outputs

oOversampling outputs buffer handling on the module

oExample

oTM5 Bus input delay

oControlling the oversampled outputs

General Information on Oversampled Outputs

The oversampled output functionality on the module can be used via the I/O mapped registers of the Sercos III module.

To enable the evaluation of the output variables on the module, the parameter OutputsAc­tiveSet (Bus Interface TM5NS31) has to be set to on / 1.

The parameter OutputsActive will then switch to on / 1 after the outputs are active on the module.

Initializing the Handling of the Oversampled Outputs

Oversampling Outputs Buffer Handling on the Module

The TM5SDM8DTS module has a circle buffer with 256 entries for each oversampled output channel.

Every 1/8 cycle, the oversampling unit switches to the next entry inside the buffer and copies the buffer position into the I/O mapped OversampleInputCycle if OversampleEnable is set (in OversampleControl).

To write new values to the buffer, you have to set the OversampleOutputCycle value.

The value is the buffer address which is intended to be written to with the output values.

In addition, OversampleOutput0xSample1_8 must be filled with the output values to write to this buffer address.

The destination addresses that you provide to the OversampleOutputCycle cannot exceed the present address +128.

This is called oversampled output window.

If the OversampleOutputCycle is greater than the present buffer address +128, the module raises an OutputCopyError flag.

If you set the OversampleControlCopyActive, the unit writes the value of the entry to the physical output channel and marks the entry as used.

If the output unit comes to an entry that is marked as used and you have set the Oversample­ControlCopyActive (in OversampleControl), the output unit sets the physical output channel to 0 and raises the OutputControlError flag.

NOTE: This detected error flag also occurs if it has been set and you unset it during program execution.

Example

The following graphic presents an example of the handling of OversampleInputCycle / OversampleOutputCycle and OversampleOutput0xSample1_8.

oAfter setting OversampleEnable to 1, the module begins to copy the buffer position to the real-time data (in cycle n–1).

oThe real-time data is read by the Sercos III master in cycle n.

oThen the data is available in the next tasks cycIe.

oThe task then calculates the buffer position for the sample data by OversampleOutputCycle = OversampleInputCycle +  80.

oIn addition, the sample data OversampleOutput0xSample1_8 for the respective output channel is set with a pattern.

oThis data is copied into the next Sercos III real-time data.

oThe data is available one cycle later in the bus interface and the module.

oThen the module copies the eight bits OversampleOutput0xSample1_8 to the OversampleOutputCycle position in the buffer.

NOTE: You must calculate the number of cycles to wait before you set the OversampleControl­CopyActive bit in the OversampleControl byte. As you see in the example graphic, the formula is the following: Number of cycles to wait before setting the OversampleCopyActive bit to 1 = (OFFSET - (5 cycles x 8 entries per cycle)) / 8 entries per cycle

Usage of OversampleInput/OutputCycle

 

 

Verify that:

oOversampleControlCopyActive is not activated before the output unit is reaching buffer address 83; otherwise an OutputControlError is detected.

oOversampleOutputCycle is not less than OversampleInputCycle + 56.

This time is needed for reading in the OversampleInputCycle from the unit in the module -> Slice RT data -> BC RT data -> sIII RT data -> tasks process data and writing Oversample­OutputCycle back down to the modules oversampling unit.

oOversampleOutputCycle is not greater than the active buffer entry position +128; otherwise an OutputCopyError is detected.

TM5 Bus Input Delay

For handling the oversampled outputs, it is necessary to know the delay between latching the inputs from the hardware and the beginning of the next Sercos cycle.

This delay in μs is shown in the TM5 bus interface parameter TM5BusInputDelay after Sercos phase up.

The parameter TM5BusInputDelay in the TM5 bus interface (TM5NS31) Devices tree object shows the delay between the input latch time and the beginning of the next RTP process cycle.

The length of one TM5 bus cycle has to be added to the result of the parameter if the input delay on the module has to be calculated because the TM5SDM8DTS module needs an extra TM5 cycle to latch the input data.

This depends on the hardware of this module. To get the time when the OversampledIn­putCycle read by your program was active, you can use the formula:

TM5BusInputDelay + [TM5 cycle time in μs]

Controlling the Oversampled Outputs

Oversample outputs support the output of an 8-bit pattern per cycle.

Each bit represents 1/8 of a cycle and is set active for cycle time in μs / 8.

For handling the oversampled outputs, the following I/O variables are relevant:

OversampleControl

OversampleControl

oOversampleEnable

oOversampleControlCopyActive

With the OversampleControl bits, the oversampling mechanism of the module is activated.

To enable the functionality, bit 0 (OversampleEnable) has to be set.

After setting bit 0 to 1, the module begins to read from its circle buffer.

The module copies its position inside the buffer to the OversampleInputCycle variable.

Then set OversampleOutputCycle to OversampleInputCycle + OFFSET in every cycle.

The module reads eight bits from the buffer in every cycle. This leads to an increase of 8 in the OversampleInputCycle per cycle.

With the cyclic operation OversampleOutputCycle = OversampleInputCycle + OFFSET, the buffer address is also increased by eight (see example).

ErrorState / ErrorQuit

ErrorState

oOutputControlError

oOutputCopyError

The OutputControlError bit is set if the module did not receive new data in time, meaning that a bit that has already been output would have been output again. The OutputCopyError bit is set if the oversampling output data could not be copied to the output control buffer. For more details, refer to Oversampling Outputs Buffer Handling on the Module.

ErrorQuit

oQuitOutputControlError

oQuitOutputCopyError

The QuitOutputControlError and QuitOutputCopyError bits can be used to reset the respective detected errors on the module.

OversampleInputCycle / OversampleOutputCycle

The OversampleInputCycle is the address in the buffer, where the oversampling unit in the module reads the last bit value from.

The OversampleOutputCycle is the address in the buffer, where the OversampleOut­put0xSample1_8 are written to.

OversampleOutput0xSample1_8

The parameters have the following physical channel mapping on the module (refer to General Information on TM5SDM8DTS):