TM5SDI2DF

Introduction

The TM5SDI2DF expansion electronic module is a 24 Vdc input electronic module with 2 fast inputs.

For further information, refer to TM5SDI2DF Electronic Module 2DI 24 Vdc Sink 3-Wire.

TM5 Module I/O Mapping Tab

Variables can be defined and named in the TM5 Module I/O Mapping tab. Additional information such as topological addressing is also provided in this tab.

Refer to the following paragraphs:

oStatus Mapping, for the status bits configuration details.

oInput Mapping, for the input parameters configuration details.

For further generic descriptions, refer to User-Defined Parameters Tab Description.

Status Bit Mapping

This table describes the TM5SDI2DF status bit mapping configuration:

Channel

Type

Description

ModuleOK

BYTE

State of the compact I/O and electronic modules

DcOk

BOOL

Voltage range:

o0: Invalid

o1: Valid

reserved

BOOL

Reserved.

NetworkOk

BOOL

TM5 bus:

o0: Bus error

o1: OK

I/O Data valid

BOOL

Data validity:

o0: Valid

o1: Invalid

reserved

BOOL

Reserved

reserved

BOOL

Reserved

reserved

BOOL

Reserved

reserved

BOOL

Reserved

Input Mapping

This table describes the TM5SDI2DF input mapping configuration:

Channel

Type

Description

DigitalInputs

DigitalInput 0-1

BYTE

State of all inputs

DigitalInputs00

BOOL

State of input 0

DigitalInputs01

BOOL

State of input 1

Counter00 

UINT

Event counter or gate measurement

Counter01 

UINT

Event counter or gate measurement

For further generic descriptions, refer to I/O Mapping Tab Description.

User-Defined Parameters Tab

This table describes the TM5SDI2DF user-defined parameters configuration:

Name

Value

Default Value

Description

InputFilter

0...127

10

Specifies the filter time of all digital inputs, adjustable in steps of 100 µs.

Counter Mode

2 counter modes can be used with the TM5SDI2DF electronic module:

oEvent counter operation - consists of transferring the counter status, registered with a fixed offset with respect to the bus cycle, and is transferred in the same cycle.

NOTE: The rising edges are registered on the counter input.

oGate measurement - consists of using an internal frequency to register the necessary time to reach the gate input.

The following figure describes the gate measuring principle

G-SE-0017802.1.gif-high.gif

:

The TM5SDI2DF value is defined by the following equation:

G-SE-0017803.1.gif-high.gif

Where:

SP = Size of Pulse to be measured.

VT = Value of TM5SDI2DF.

CF = Clock Frequency.

For example: For a Clock Frequency at 3 Mhz and a Size of Pulse to be measured = 15 ms, the value of TM5SDI2DF is near 45000.

NOTE:

oOnly one of the counter channels can be used for gate measurement at any one time.

oThe time between rising and falling edges for the gate input is registered using an internal frequency. The result is verified for overflow (FFFF hex).

oThe recovery time between measurements must be  > 100 µs.

oThe measurement result is transferred with the falling edge to the result memory.

The following table gives the maximum Size of Pulse to be measured depending on the Count Frequency parameter:

Maximum Size of Pulse

Clock Frequency

13.653125 ms

48 MHz

27.30625 ms

24 MHz

54.6125 ms

12 MHz

109.225 ms

6 MHz

218.45 ms

3 MHz

436.9 ms

1.5 MHz

873.8 ms

0.75 MHz

1747.6 ms

0.375 MHz

3542.432432 ms

0.185 MHz

For example: For a Clock Frequency at 48 Mhz, the maximum Size of Pulse to be measured = 13 ms.

Additional Function Input Latch

Using this function, the positive edges of the input signal can be latched with a resolution of 200 µs. With the “Acknowledge - input latch” function, the input latch is either reset or prevented from latching.

It works in the same way as a dominant reset RS flip-flop:

R: Status03

S: Status02

Q

Status

0

0

x

Do not change

0

1

1

Set

1

0

0

Reset

1

1

0

Reset