The module has 2 functioning modes:
oSynchronous
oAsynchronous
The ADC is synchronously read with the TM5 Bus when:
oThe bits 0...3 of the ADC Configuration Register ConfigOutput00 are set with the value 1110 hex.
oThe ADC cycle time is ≥ 1/4 the TM5 Bus cycle time. For further information, refer to Analog Input Register.
oThe ADC cycle time is a multiple integer of the configured cycle time of the TM5 Bus.
NOTE: AnalogInput00 is set to FF80 0000 hex if the electronic module is configured with values outside these limits.
When the ADC is asynchronously read with the TM5 bus, the electronic module attempts to maintain to the set ADC cycle time as closely as possible without being synchronized to the TM5 Bus and the bit 2 of StatusInput00 is set to 1(see Status Input Register table).
The following table describes the jitter, down time and settling time:
|
Characteristics |
Values |
|
|---|---|---|
|
Jitter |
ADC cycle times <1500 μs |
± 1 μs max. |
|
ADC cycle times >1500 μs |
± 4 μs max. |
|
|
Down time on the TM5 Bus |
50 μs + (TM5 Bus cycle time/128) |
|
|
Settling time 1 |
150 x TM5 Bus cycle time |
|
|
1 The settling time is the time between the falling edge of the valid bit (bit 0 in the status register) and the falling edge of the ADC synchronous bit (bit 2 in the status register). |
||
